1. Field of the Invention
The present invention generally relates to pipeline processor architecture, and more specifically to delaying a load miss flush and the attendant re-fetching and re-execution.
2. Description of the Related Art
Microprocessor developers have for decades relied on a blend of increasing transistor density and improved architectural efficiency to obtain ever higher throughputs for modern microprocessors. Among the architectures that have been useful is the pipeline architecture, where discrete functional units perform allocated tasks generally in sequence.
One technique that generally improves pipelined processor performance is speculatively assuming that an access to memory, or load, occurs by successfully retrieving the data from a responsive cache. Thus, most of the time, an instruction is prepared for executing just as the memory delivers the data or operand. Unfortunately, occasionally the targeted data does not reside in the cache, and the memory unit issues to the pipeline processor a “load miss” signal.
Microprocessor designers have employed several techniques, or backing mechanisms, to handle the situation when the assumption fails. One such backing mechanism is to restart after the load instruction, which did not finish on time. When both a level one and a level two cache miss occurs, it may take over 100 processor cycles to wait for a load instruction to complete by retrieving data from off-chip.
Another backing mechanism provides expensive instruction flush tagging mechanisms to restart the dependent instruction. The tagging mechanisms tend to occupy a lot of area on a microprocessor die.